This invention relates generally to semiconductors, and more specifically, to the formation of planar surfaces in semiconductor devices.
A common requirement in semiconductor processing is the formation of structures that have a planar exposed surface. When surfaces are not planar, subsequent processing steps usually can be detrimentally affected. For example, when surfaces are not planar and a subsequent etch step is required, variable amounts of material are removed resulting in structures that are not desired. A common technique that is used to planarize a surface is the use of a chemical mechanical polish (CMP). The CMP process is a mechanical/chemical process that uses a rotating pad in conjunction with a slurry solution to physically remove material from an exposed device surface. Known CMP processes usually remove material for a pre-programmed time period or until an endpoint is optically detected. However, even the most sophisticated CMP processes do not evenly remove material from a surface. A common phenomenon is the dishing or erosion of portions of the surface so that the polished structure is uneven and non-planar.
Because the CMP process is imperfect, others have proposed the use of CMP with chemical etch steps. However, etch steps add cost and processing time to the manufacture of a semiconductor. Multiple manufacturing tools are, required to implement surface planarization when etching is required in combination with CMP. Further, CMP processing may have to be implemented both before and after the etching steps. Yet another planarization technique is the use of a planar fill layer overlying a nonplanar structure. The planar fill layer may be polished to a predetermined height that results in a planar upper surface. However, in forming the planar fill layer the device may be exposed to detrimentally high temperature to form the planar fill layer and the planar fill layer may itself have high defectivity.